1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of insulating gate elements and a manufacturing method thereof. In particular, the invention involves an improvement in simultaneous realization of high-speed operation, long lifetime and the ease of manufacturing method.
2. Description of the Background Art
In semiconductor devices, such as LSIs with a plurality of MOS transistors, there are, for example, employed plural types of gate voltages for MOS transistor. In a certain type of DRAM, two types of MOS transistors of different gate voltage are provided on a memory cell and a peripheral circuit. Since the memory cell is required to instantly charge or discharge electric charge to a capacitor therein, a gate voltage higher than that to the peripheral circuit is applied.
FIG. 40 is a cross-sectional view of a conventional semiconductor device having two types of MOS transistors of different gate voltage as described above. In the conventional semiconductor device 151, a high-voltage element H to which a high gate voltage is applied, and a low-voltage element L to which a gate voltage lower than that to the element H is applied, are formed in a single semiconductor substrate 71. The elements H and L are both MOS transistors and are electrically isolated from other elements adjoining them, by an element isolator 76 formed in the upper major surface of the substrate 71.
In the upper major surface of the substrate 71, P type wells 72 and 82 extend over the entire regions of the elements H and L, respectively, around the element isolator 76. N type source/drain regions 73 and 83 are selectively formed on the exposed surfaces of the P type wells 72 and 82, respectively, around each central portion of the exposed surfaces. Gate insulating films 77 and 87 overlie their respective central portions, and gate electrodes 79 and 89 overlie the gate insulating films 77 and 87, respectively. A source electrode 80 and a drain electrode 81 are connected to the exposed surface of the source/drain regions 73. Similarly, a source electrode 90 and a drain electrode 91 are connected to the exposed surface of the source/drain region 83.
Since a high gate electrode is applied to the high-voltage element H, an electric field higher than that to the low-voltage element L is applied to the gate insulating film 77. Therefore, the gate insulating film 77 is required to have a thickness of large enough to withstand such a high electric field and to suppress the aged deterioration that is closely related to the electric field. On the other hand, the gate insulating film 87 is not required to be so thick as the gate insulating film 77 because the electric field applied thereto is low.
In cases where a device 151 is a DRAM, a high-voltage element H belongs to a memory cell, and a low-voltage element L belongs to a peripheral circuit, the element L is not required to withstand so high gate voltage as the element H, but required to have a high current driving capability in order to realize high-speed operation. In general, the current driving capability of MOS transistors increases with decreasing thickness of a gate insulating film.
Unfortunately, since in the semiconductor device 151 the gate insulating film 87 of the low-voltage element L has the same thickness as the gate insulating film 77, there are more margin than is necessary for suppressing the aged deterioration and ensuring a long lifetime, while it fails to exhibit a sufficient current driving capability to be a factor which can inhibit high-speed operations. Thus, with the device 151, the long lifetime and high-speed operation compatibility is not accomplished.
This problem can arise not only when a device 151 is configured as a DRAM, but also when it is other semiconductor device. For example, In semiconductor devices having an exterior power input portion that receives the input of an external power voltage to generate, as an internal voltage, a power voltage lower than the external power supply voltage, a relatively high voltage is applied to MOS transistor that belongs to the external power input portion, as a gate voltage, and a relatively lower voltage is applied to MOS transistor that receives the supply of an internal power supply.
To overcome this problem, as shown in FIG. 41, there has been proposed a semiconductor device 152, which is referred to as "dual oxide" type. In the device 152, a gate insulating film 92 of a low-voltage element L is thinner than a gate insulating film 77 of a high-voltage element H. That is, all elements do not have a uniform gate insulating film thickness. The thickness is set individually, depending on the necessary breakdown voltage and current driving capability. Therefore, the high-voltage element H insures a high breakdown voltage and a long lifetime, and the low-voltage element L insures a high current driving capability, thereby establishing the long lifetime and high-speed operation compatibility.
Unfortunately, the semiconductor device 152 has another problem that as shown in the manufacturing steps in FIGS. 42 to 47, its manufacturing method is not easy and thus difficult to put it into practice. To obtain a device 152, firstly the step shown in FIG. 42 is conducted. Specifically, after a semiconductor substrate 71 is prepared, an element isolator 76 and wells 72 and 82 are formed in the upper major surface of the substrate 71. The wells 72 and 82 are respectively formed in the region whereat it is desired to form a high-voltage element H or a low-voltage element L in the regions surrounded by the element isolator 76.
Referring to FIG. 43, insulating films 93, 94 are formed over the upper major surface of the semiconductor substrate 71, i.e., over the entire exposed surfaces of the wells 72 and 82, respectively.
Referring to FIG. 44, there is formed a shield 95 that has an opening in the insulating film 93 and selectively covers the insulating film 94.
Referring to FIG. 45, an insulating film is further stacked on the portion as not being shielded by the shield 95, i.e., on the insulating film 93. As a result, the insulating film 93 is selectively thickened, whereas the insulating film 94 remains as it is.
Referring to FIG. 46 and 47, after the shield 95 is removed, gate electrodes 79 and 89 are formed on the insulating films 93 and 94, respectively.
Thereafter, N type impurity is selectively implanted with the gate electrodes 79 and 89 acting as a shield (this step is not shown), so that source/drain regions 73 and 83 are selectively formed on the exposed surfaces of the wells 72 and 82, respectively, as shown in FIG. 41. Then, a source electrode 80 and a drain electrode 81 are formed on the exposed surfaces of source/drain regions 73 so as to surround the gate electrode 79. At the same time, a source electrode 90 and a drain electrode 91 are formed on the exposed surfaces of source/drain regions 83 so as to surround the gate electrode 89, resulting in a semiconductor device 152.
As set forth above, in manufacturing a device 152, it is necessary to form a gate insulating film 77 through two-stage process in which a shield 95 having a selective opening is formed and then employed as described. This complicates the manufacturing steps, and it seems to be difficult to put it into practice because of problems involved in yield.